The design and manufacture of application specific integrated circuits (ASICs) has become a significant segment of the semiconductor industry. The two primary methods of designing ASICs employ gate arrays and cell libraries. Gate array based circuits are integrated circuits with a predefined set of components at predefined positions on a semiconductor die. Specific applications are implemented by interconnecting the predefined components so as to perform a specified set of functions. Cell based circuits are integrated circuits that are formed using cells selected from one or more cell libraries. A cell library is a set of predefined components that can be placed at any specified position on a semiconductor die and then interconnected so as to perform a specified set of functions. While there are other technologies used for designing ASICs, the present invention is primarily concerned with automatically routing the interconnections between components in cell based or gate array based circuits.
To quickly and efficiently design cell based and array based circuits, it is important to be able to quickly and accurately form or route the connections between the components of a specified circuit To this end, there are number of automatic routing schemes which are used in prior art products, and which have been disclosed in prior art publications.
The present invention solves one particular problem associated with the prior art routing schemes. More specifically, the problem addressed by the present invention concerns routing interconnections through non-rectangular routing regions Looking at the circuit layout 180 shown in FIG. 5, it is standard procedure to divide the routing regions 190, 192 and 194 into two channels: one channel comprising regions 190 and 192, and a second channel comprising region 194. Due to standard limitations placed by prior art CAD systems on the positions that interconnections can cross the boundaries between channels, the connection between terminals 184 and 186 will typically have the shape of connection line 182. Clearly, connection line 182 is much longer than the shortest possible interconnection line between terminals 184 and 186.
The present invention provides a method of creating and routing "special channels" which results in shorter interconnection lines and improves the quality of the layout of integrated circuits.